Substrates on which an electronic device are electrically mounted are commonly fabricated from dielectric materials such as ceramics, ceramic metal composites, polymeric materials and polymeric material-metal composites. These substrates can have multi-level electrical conductor patterns embedded therein.
In the simplest embodiments, the substrate has one dielectric layer having electrical conductor patterns on both sides thereof which are electrically interconnected by a plurality of electrically conducting apertures or vias extending through the substrate.
In an alternative embodiment, the substrate is fabricated from an electrically and/or thermally conducting layer coated with a dielectric material. A plurality of through-holes are drilled, punched or etched through the substrate. To form an electrically conducting aperture or via which is electrically isolated from the core, the through-holes are typically plated with an electrically conductive layer and then filled at least in the region of the core with an electrically insulating material.
However, the techniques employed for filling the vias require subsequent planarization so as to ensure that the surfaces are planar whereby the dielectric is flush or level with the metallization thereon. However, various of these prior art planarization methods introduce dimensional changes to the printed circuit board or adversely impact its dimensional stability. Planarization is normally done by belt-sanding and/or chemical polishing method which include mechanical deformation or stretching to the printed circuit board. Such dimensional changes affect subsequent circuitization processes.
Accordingly, continuing efforts are underway for providing improved techniques for filling apertures in printed circuit boards.